Espressif Systems /ESP32 /SLC /_1INT_ENA

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Interpret as _1INT_ENA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FRHOST_BIT8_INT_ENA)FRHOST_BIT8_INT_ENA 0 (FRHOST_BIT9_INT_ENA)FRHOST_BIT9_INT_ENA 0 (FRHOST_BIT10_INT_ENA)FRHOST_BIT10_INT_ENA 0 (FRHOST_BIT11_INT_ENA)FRHOST_BIT11_INT_ENA 0 (FRHOST_BIT12_INT_ENA)FRHOST_BIT12_INT_ENA 0 (FRHOST_BIT13_INT_ENA)FRHOST_BIT13_INT_ENA 0 (FRHOST_BIT14_INT_ENA)FRHOST_BIT14_INT_ENA 0 (FRHOST_BIT15_INT_ENA)FRHOST_BIT15_INT_ENA 0 (SLC1_RX_START_INT_ENA)SLC1_RX_START_INT_ENA 0 (SLC1_TX_START_INT_ENA)SLC1_TX_START_INT_ENA 0 (SLC1_RX_UDF_INT_ENA)SLC1_RX_UDF_INT_ENA 0 (SLC1_TX_OVF_INT_ENA)SLC1_TX_OVF_INT_ENA 0 (SLC1_TOKEN0_1TO0_INT_ENA)SLC1_TOKEN0_1TO0_INT_ENA 0 (SLC1_TOKEN1_1TO0_INT_ENA)SLC1_TOKEN1_1TO0_INT_ENA 0 (SLC1_TX_DONE_INT_ENA)SLC1_TX_DONE_INT_ENA 0 (SLC1_TX_SUC_EOF_INT_ENA)SLC1_TX_SUC_EOF_INT_ENA 0 (SLC1_RX_DONE_INT_ENA)SLC1_RX_DONE_INT_ENA 0 (SLC1_RX_EOF_INT_ENA)SLC1_RX_EOF_INT_ENA 0 (SLC1_TOHOST_INT_ENA)SLC1_TOHOST_INT_ENA 0 (SLC1_TX_DSCR_ERR_INT_ENA)SLC1_TX_DSCR_ERR_INT_ENA 0 (SLC1_RX_DSCR_ERR_INT_ENA)SLC1_RX_DSCR_ERR_INT_ENA 0 (SLC1_TX_DSCR_EMPTY_INT_ENA)SLC1_TX_DSCR_EMPTY_INT_ENA 0 (SLC1_HOST_RD_ACK_INT_ENA)SLC1_HOST_RD_ACK_INT_ENA 0 (SLC1_WR_RETRY_DONE_INT_ENA)SLC1_WR_RETRY_DONE_INT_ENA 0 (SLC1_TX_ERR_EOF_INT_ENA)SLC1_TX_ERR_EOF_INT_ENA

Fields

FRHOST_BIT8_INT_ENA
FRHOST_BIT9_INT_ENA
FRHOST_BIT10_INT_ENA
FRHOST_BIT11_INT_ENA
FRHOST_BIT12_INT_ENA
FRHOST_BIT13_INT_ENA
FRHOST_BIT14_INT_ENA
FRHOST_BIT15_INT_ENA
SLC1_RX_START_INT_ENA
SLC1_TX_START_INT_ENA
SLC1_RX_UDF_INT_ENA
SLC1_TX_OVF_INT_ENA
SLC1_TOKEN0_1TO0_INT_ENA
SLC1_TOKEN1_1TO0_INT_ENA
SLC1_TX_DONE_INT_ENA
SLC1_TX_SUC_EOF_INT_ENA
SLC1_RX_DONE_INT_ENA
SLC1_RX_EOF_INT_ENA
SLC1_TOHOST_INT_ENA
SLC1_TX_DSCR_ERR_INT_ENA
SLC1_RX_DSCR_ERR_INT_ENA
SLC1_TX_DSCR_EMPTY_INT_ENA
SLC1_HOST_RD_ACK_INT_ENA
SLC1_WR_RETRY_DONE_INT_ENA
SLC1_TX_ERR_EOF_INT_ENA

Links

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